For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. A concise summary of near-term and long-term challenges to continued complementary metal oxide semiconductor (CMOS) scaling can be found in the “Grand Challenges” section of the 2002 Update of the International Technology Roadmap for Semiconductors (ITRS). A very thorough review of the device, material, circuit, and systems can be found in Proc. IEEE, Vol. 89, No. 3, March 2001, a special issue dedicated to the limits of semiconductor technology.
Since it has become increasingly difficult to improve MOSFETs and therefore CMOS performance through continued scaling, methods for improving performance without scaling have become critical. One approach for doing this is to increase carrier (electron and/or hole) mobilities. Increased carrier mobility can be obtained, for example, by introducing the appropriate stress into the Si lattice.
The application of stress changes the lattice dimensions of the silicon (Si)-containing substrate. By changing the lattice dimensions, the electronic band structure of the material is changed as well. This results in changes in carrier transport properties, which can be dramatic in certain cases. The application of stress can be used to enhance the performance of devices fabricated on the Si-containing substrates.
Compressive longitudinal stress along the channel increases drive current in p-type field effect transistors (pFETs) and decreases drive current in n-type field effect transistors (nFETs). Tensile longitudinal stress along the channel increases drive current in nFETs and decreases drive current in pFETs.
Nitride liners positioned atop field effect transistors (FETs) have been proposed as a means to provide stress based device improvements. Referring to FIG. 1, a prior field effect transistor (FET) 19 is provided including a nitride liner 15 positioned on a gate region 5 having permanent spacers 14, in which the nitride liner 15 produces a stress on the device channel 12. The device channel 12 is located between source/drain regions 6 and source/drain extension regions 7. The source/drain regions 6 further comprise silicide regions 11. The gate region 5 includes a polysilicon gate 3 atop a gate dielectric 2. The gate region 5 further comprises a gate cap 8. The stress transfer in this prior FET 19 is limited since the nitride liner 15 is relatively far away from the gate 3 due to the presence of the permanent spacers 14. Typically, the channel stress produced by the nitride liner 15 in this prior art structure ranges from about 100 MPa to about 200 MPa.
One proposal for increasing the stress produced in the device channel 12 of the above described device is to increase the thickness of the nitride liner 15. In order to increase the stress produced in the device channel 12 in this approach by a magnitude of two, the thickness of the nitride liner 15 must also be increased by roughly a magnitude of two. This approach is unacceptable since it limits the scaling of the distance between the contact 50 and the gate conductor 3. Another proposal for increasing the stress produced within the device channel 12 is to increase the intrinsic stress within the nitride liner 15 itself. This approach is also unacceptable because it requires additional processing and has negative effects on the portions of the device in which a stress in not desired.
Further scaling of semiconducting devices requires that the stress levels produced within the substrate be controlled and that new methods be developed to increase the stress that can be produced.